14.23 TagLo (28) and TagHi (29) Registers

CacheOp is Index Load/Store Data

This section describes the following three states of the TagLo and TagHi registers, when the CacheOp is an Index Load/Store Data:

Primary Instruction Cache Operation

If the CacheOp is an Index Load/Store Data for the primary instruction cache, the TagHi register stores the most significant four bits of a 36-bit instruction, as shown in Figure 14-31; the rest of the instruction is stored in the TagLo register.



Figure 14-31 TagHi/Lo Register Fields in Primary Instruction Cache
When CacheOp is Index Load/Store Data

0: Reserved. Must be written as zeroes, and returns zeroes when read. (See page 224 of Errata.)

Primary Data Cache Operation

If the CacheOp is Index Load/Store Data for primary data cache, the TagHi register is not used. The TagLo registers contains a 32-bit data word for the cache operation, as shown in Figure 14-32.



Figure 14-32 TagHi/Lo Register Fields in Primary Data Cache
When CacheOp is Index Load/Store Data

Secondary Cache Operation

If the CacheOp is Index Load/Store Data for the secondary cache, a doubleword of data is required for the CacheOp. The TagHi register stores the upper 32 bits of the doubleword and the TagLo register stores the lower 32 bits, as shown below in Figure 14-33.



Figure 14-33 TagHi/Lo Register Fields in Secondary Cache
When CacheOp is Index Load/Store Data

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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